Conventional semiconductor devices and related EDA tools/libraries are mostly based around CMOS logic circuits.
CMOS uses complementary n-type and p-type transistors, and displaced the previous NMOS (n-type) technologies in the 1980s due to better power efficiency, higher noise margin, improved fan-out and easier integration. However, in flexible electronics NMOS is currently state-of-the-art and the lack of robust CMOS capability is a critical issue. In flexible electronics significant effort has been put into both NMOS and PMOS but there is a mismatch in achievable performance (e.g. mobilities). Complementary materials require very different deposition and patterning processes (e.g. solution-deposition vs. vacuum-deposition), thus combining the two into a single manufacturable process is very challenging.
The main building block for digital logic is the inverter. Three main inverter variants of NMOS logic can be implemented.
FIG. 1a shows three prior art implementations of NMOS inverters, and FIG. 1b shows a prior art CMOS inverter. The CMOS inverter flips between the PMOS and NMOS devices being active, such that they complement each other and minimal leakage at 0V.
The three NMOS variants, as illustrated in FIG. 1a, all have benefits and drawbacks (footprint, power efficiency, noise margin), and are used today in “Flexible Electronics” due to the absence of a commercially viable manufacturing route to CMOS. However, this limits the ease of design as well as the degree of integration and complexity that can be achieved. Noise margin dictates the number of logic gates which can be cascaded, i.e. the complexity of the overall circuit. This is sensitive to variations in threshold voltage (the voltage at which the transistor turns-on) and channel-length (as channel-length reduces to minimise footprint the noise margin is lower).
FIG. 2a illustrates that as the variation in threshold voltage (□VT) for PMOS increases the yield of gates (n) drops (□VT˜0.15V is a reasonable production benchmark; the same is true for NMOS as PMOS); FIG. 2b illustrates that CMOS (C-TFT) is able to yield significantly higher numbers of gates (stages) than PMOS (P-TFT) even with a relatively large variation in threshold voltage (□VT˜0.5V)(see IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 4, APRIL 2006 601, “Influence of Transistor Parameters on the Noise Margin of Organic Digital Circuits”, Stijn De Vusser, Jan Genoe, and Paul Heremans, and IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 1, JANUARY 2010 201, “Noise-Margin Analysis for Organic Thin-Film Complementary Technology”, Dieter Bode, Cédric Rolin, Sarah Schols, Maarten Debucquoy, Soeren Steudel, Gerwin H. Gelinck, Jan Genoe, and Paul Heremans).
FIG. 3 illustrates another prior art logic gate implemented in CMOS, namely a NAND gate. Two PMOS transistors are connected in parallel between the output terminal and first supply rail (Vdd), each of these transistors receiving a respective one of inputs A and B. Two NMOS devices are connected in series between the output terminal and a second supply rail (ground, or Vss in this example), each also receiving a respective one of inputs A and B.